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a few days ago, I read about the uP21, a 20 bit stack architecture. I find 20 bit to be an interesting and weird size, not being a multiple of ...
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    20 bit architecture


    a few days ago, I read about the uP21, a 20 bit stack architecture. I find 20 bit to be an interesting and weird size, not being a multiple of 8. I do think the advantage is more addressable memory (1M words, the word size I believe is also 20 bits instead of the typical 8 bit byte), however some operands would be weird for that size. They talk of 16 bit graphics, or 24 or 32, but not 20 bits as a pixel color value. 20 bit Unicode characters? 1M would be perfect for all the Chinese and every other crazy thing those freaks are trying to put into the character set, but isn't 64K enough if you have sanity when designing a character set? (Although I know in theory there are more than 64K Chinese characters, seriously who uses more than half of them anyway? Most only use about 2000 of them.) Anyway though wouldn't 20 bits be awkward for interfacing with some hardware, such as flash hard drives? Don't things like that have block boundaries and data paths in multiples of 16 or 8 bits?

    Anyway of course there's always the standard 16 bits, the question being if 64K words (if 16 bit word size = 128 KB) is enough for various embedded systems.

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    128KB is enough for some embedded systems, but you would have to be running a custom kernel, or micro-kernel OS to do anything reasonable with that these days. Now, a 32-bit CPU w/ 64MB of RAM is not uncommon, and can pretty much fit on one or two chips.
    Sometimes, real fast is almost as good as real time.
    Just remember, Semper Gumbi - always be flexible!

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    Linux Guru Rubberman's Avatar
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    As for wierd word sizes, think about the old DEC 10/20 architecture - 36 bits! Hence the old geek saying "If you aren't dealing 36 bits, then you aren't dealing with a full DEC"!
    Sometimes, real fast is almost as good as real time.
    Just remember, Semper Gumbi - always be flexible!

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    Well yea but how would you interface with say a flash hard drive that way? You have 20 bits in your words but 16 or 8 bits in your words on the hard drive, how does one deal with that?

    I was also thinking using (for design purposes, far far away from implementing except perhaps as an emulator) a 16 bit architecture using bank switching, having 16 hardware processes with a 4 bit register/latch to switch between them on a context switch. This is NOT the same as the x86 segment:offset model, the banks of 64k words are separate. Total 1M words of 16bits (2 MB). So each process has access to 64k words of memory, if needed could do threads within those. Is any of this practical? Again think embedded or small scale computer (ie cell phone).

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    Linux Guru Rubberman's Avatar
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    You can design a computer architecture just about any way you want. There are some good books on the subject, though they tend to be a bit pricey. For some interesting architectures, check out VLIW computers (Very Long Instruction Word) such as Wave Tracer. So, this is an engineering exercise in effect. My advice would be to invest a bit in a good modeling/simulation environment and start playing with your design elements. I use Sparx Enterprise Architect for this sort of work. I've used it to design some very complex systems.
    Sometimes, real fast is almost as good as real time.
    Just remember, Semper Gumbi - always be flexible!

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    Also, I was considering a memory to memory architecture. Using 16 bit everything. Operands would be offsets from a data pointer and would fit in 4 bits. So an instruction could be like 4 bit opcode, 4 bit operand, 4 bit operand, 4 bit destination operand for the ops anyway that take two things and a destination. Not much in the way of extra hardware other than an on chip memory (128 KB, very reasonable to put on a chip these days...). Also this way, I could even have two memories, one for data, one for instructions, basically a Harvard architecture. Advantages I can think of would be no more juggling around registers and no overhead for load/store. Is this practical? Like in constrast to stack machines, with some algorithm scratch papering I found I was juggling stuff between the two stacks quite a bit to get things done; those conceptual instructions add overhead both in number of instructions and in conceptual mind boggling, I can't see the problem for what it is.

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