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Thread: 2 Ported SRAM help
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- Join Date
- Nov 2010
2 Ported SRAM help
I am working on a problem involving the attached picture.
For reads there is a sense amp out delay of 1ns, a output delay of 3ns, and a row/word select delay of 2ns all totaling 6 ns. If I was trying to find total delay is this the correct number or should I take into account all 4 sense amp delays which would mean the sense amp delay would be 4 instead of 1 and same with the output would that be 4x as well?
The next part of the question involves read bandwidth of 440 MB/sec and asks if this array is sufficient however before I can answer that question I need to know if I am calculating the delay correctly.
Any help you can give would be awesome.
- Join Date
- Apr 2009
- I can be found either 40 miles west of Chicago, in Chicago, or in a galaxy far, far away.
I'm sure SOMEONE can answer that, but they need to be a memory chip engineer I think! I assume this is a class assignment question?Sometimes, real fast is almost as good as real time.
Just remember, Semper Gumbi - always be flexible!