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Background story: I noticed that my hard drive was really slow. In the dmesg it said that I had a 40-pin PATA cable, so I bought an ATA133 (80-pin, ROLINE ...
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- 04-19-2010 #1
- Join Date
- Jun 2008
PATA Maxtor 6L080L0, max UDMA/133, but configured for UDMA/100
Motherboard: MSI P965 Neo2
[ 1.584390] eth0: RTL8169sc/8110sc at 0xffffc90000376c00, 00:19:db:63:29:fc, XID 18000000 IRQ 21 [ 1.596949] ahci 0000:03:00.0: version 3.0 [ 1.600330] pata_marvell 0000:03:00.0: PCI INT A -> GSI 17 (level, low) -> IRQ 17 [ 1.600360] pata_marvell 0000:03:00.0: setting latency timer to 64 [ 1.600645] scsi4 : pata_marvell [ 1.600746] scsi5 : pata_marvell [ 1.600780] ata5: PATA max UDMA/100 cmd 0xdc00 ctl 0xd880 bmdma 0xd400 irq 17 [ 1.600782] ata6: PATA max UDMA/133 cmd 0xd800 ctl 0xd480 bmdma 0xd408 irq 17 [ 1.801983] ata5.01: ATA-7: Maxtor 6L080L0, BAJ41G20, max UDMA/133 [ 1.801987] ata5.01: 160086528 sectors, multi 0: LBA [ 1.851931] ata5.01: configured for UDMA/100 [ 1.852014] scsi 4:0:1:0: Direct-Access ATA Maxtor 6L080L0 BAJ4 PQ: 0 ANSI: 5 [ 1.852152] sd 4:0:1:0: [sdc] 160086528 512-byte logical blocks: (81.9 GB/76.3 GiB) [ 1.852168] sd 4:0:1:0: Attached scsi generic sg3 type 0 [ 1.852252] sd 4:0:1:0: [sdc] Write Protect is off [ 1.852255] sd 4:0:1:0: [sdc] Mode Sense: 00 3a 00 00 [ 1.852276] sd 4:0:1:0: [sdc] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA [ 1.852395] sdc: sdc1 [ 1.876806] sd 4:0:1:0: [sdc] Attached SCSI disk
The cable has three connectors, one is furthest of the other two, so I connected that to the motherboard. The other two connectors are for hard drives:
(A) proximal ("nearer") to the motherboard
The PATA hard drive is connected to the (A) connector. Connector (B) is not connected.
$ modinfo pata_marvell filename: /lib/modules/2.6.32-21-generic/kernel/drivers/ata/pata_marvell.ko version: 0.1.6 license: GPL description: SCSI low-level driver for Marvell ATA in legacy mode author: Alan Cox srcversion: 2F5588AB6D0C8D4910F57D2 alias: pci:v000011ABd00006145sv*sd*bc*sc*i* alias: pci:v000011ABd00006123sv*sd*bc*sc*i* alias: pci:v000011ABd00006121sv*sd*bc*sc*i* alias: pci:v000011ABd00006101sv*sd*bc*sc*i* depends: vermagic: 2.6.32-21-generic SMP mod_unload modversions
1) Why is it limited to UDMA/100?
2) I saw an "ata6" in dmesg, it appears not to be used and has udma/133. Is that the free connector (B) of the cable?
3) If I connect it to the other connector (B), do you think it would get UDMA/133?
- 04-20-2010 #2
- Join Date
- Nov 2006
ATAs and Sync - Everything is OK now.
Normally, this behavior is normal, the initial negotiation made in the system Bios make a simple auto-negotiation to determine in wich of the frequencies ATA/IDE work. The device itself has it's support table, and to the maximum extent, determined by conditions including cable (40 Pins = 66MHz max ( some variations include a 100MHz autodetection), 80 Pins = 133 Mhz max (altough some rare variations include a 150 Mhz negotiation, but most of the time this will be resulting in problems )). Depending on conditions, they will synchronize in the maximum possible frequency.
-> Older MotherBoards use a cristal of 14,xxx to start basic clock computer frequency spread settings for the MB components, and all other devices folow, they start with 33Mhz and then a 4x IDE/ATA capable controller of 33Mhz = 133Mhz. (ATA 6)
-> New Motherboards use another Cristal, wich results in another frequencies, starting in 24,xxx Mhz, and the majority of the components have a base of 100Mhz, then, to facilitate bus engineering, they cap the multiplier of older devices atached to the same bus to 2x, when it's another IDE controller atached to the same bus and/or convert SATA to IDE in the South Bridge, resulting in a limit of 100Mhz in the IDE tip, avoiding an overclock (150Mhz) of the IDE Bus.
It's not your IDE/MB fault, but sincerely, you won't need extra Mhz since the real performance of older IDEs Read/Write does not feed 100MHz buses.
100Mhz is OK for both sides, your controller, and your HDD
Good Vibes !
- 04-20-2010 #3
- Join Date
- Jun 2008
nice and detailed explanation, thanks!