shunty123

Hi....Good Afternoon

i bought usb mass storage card from one company . the interface of my usb mass storage card with motheboard is PCI.

the Design is smthing like this......

pci-Pci Bridge --------------->pci/USB2 bridge ----------> usb2/NAND

controller----------------->NAND CHIPS.


the hardware manual of this card tells PCI Interrupt (INTB) is passed to PCI Slot.


Now i wrote the pci Device Driver to know the vendor id, device id ,int line, int pin etc... i got the vendor id ,device id but on INT LINE i am getting 0XFF; i am not able to undestand tht why i am not getting the exact IRQ for this card...

is this is correct way what i am doing if not please suggest me how to get the correct IRQ no....

thanks in advance
Mark.s

bloggins666

Have you tried to read the PCI_INTERRUPT_PIN (register 61)? If it's 0 then your device does not support interrupts.

Also, it's a longshot and highly improbably but PCI does support 256 (0xff) interrupts. Is what it's returning actually correct?

Cheers!!

shunty123

Hello Good Evening sir

thanks for reply..

I studied the pci header It is telling that "int pin" =0x01; that mean our Card support Interrupts.



[coreOS] -> pciHeaderShow (0x1000003,1,0)

PCI Configuration Header, (0x01000003,1,0)
vendor ID = 0x1131
device ID = 0x1561
command register = 0x0006
status register = 0x0210
revision ID = 0x11
class code = 0x0c
sub class code = 0x03
programming interface = 0x10
cache line = 0x08
latency time = 0xfc
header type = 0x80
BIST = 0x00
base address 0 = 0x58000000
base address 1 = 0x00000000
base address 2 = 0x00000000
base address 3 = 0x00000000
base address 4 = 0x00000000
base address 5 = 0x00000000
cardBus CIS pointer = 0x00000000
sub system vendor ID = 0x1131
sub system ID = 0x1561
expansion ROM base address = 0x00000000
interrupt line = 0xff (Default value = 0x00)
interrupt Pin = 0x01



Now i checked the hardware manual for my mass storage card. it is written in hardware manual that INTB,INTC lines are coming to pci slots from my pci/usb bridge which generates interrupts.

Now i want an IRQ no: specific to that INTB line for my mass storage card.
but i do not know the way to get the IRQ no: for This INTB line.

so please tell me how to get the IRQ number.

thanks for help

mark.S

bloggins666

Just for my own education I put the line:
pci_read_config_byte(dev,PCI_INTERRUPT_LINE,&myirq );

into a driver I'm currently working on and printed out the result. I did get what looks like a valid value of 11. I verified this by running the command "lspci -v" and seeing the device in the list of devices found on the PCI bus.

This is a released driver and it does work as an interrupt driven device but in no way does it need to know what the IRQ number is. I had to add the code to it in order to print out the information.

I guess what I'm saying is that I don't know how to get your information and I'm not even sure that you need to know what the IRQ is. The PCI bus will administer to it when your "probe" function is called and an IRQ will be allocated. Even your interrupt service routine is installed by calling the appropriate PCI API function and it will take care of it.

Sorry sir, it's a pretty inadequate answer to your problem. Good Luck.

Cheers!!

shunty123

Hi....Good Afternoon

sir actually i am not using the Intel X-86 Board and LINUX OS. i am Working on

powerPC with HPCNET8641D Board and VXworks OS.


In intel x-86 BIOS assigns the specific irq to externel cards.. i plugged my card with
motherboard in PCI Slot during Booting time it assigned irq no: 3 to my card....


but in VXworks its not like that. i think acc. to my knowledge we have to give this IRQ no manually. then we have to check whether cpu is interrupted or not .

so now still i am confused with irq numbers ....


if possible should i send the architecture of hardware ? may be then u can help me better.

bloggins666

My experience with any board that was custom built for PPC and using VxWorks was a few years ago but usually the H/W engineers would only have 1 IRQ for all h/w interrupts and then they would implement a mask register which had a bit for each device that could generate an interrupt. This implementation is fairly standard. I would certainly need your h/w architecture to figure it out but I have to point out that this is a Linux forum, not a VxWorks forum and you really should be looking for answers somwhere else. I think we are done here. Good luck.

Cheers!!