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- Join Date
- Sep 2008
gcc optimization for power through instruction rescheduling
I am trying to optimize gcc by scheduling processor instructions aimed at reducing power consumption. Though this technique primarily used for VLIW architectures so far, here i want to use this technique to solve this problem for x86-64 architecture. Power can be reduced by the product of capacitance loading and transition activity. Since bus wires have large capacitance loading, the reduction of transition activities of buses will be very effective in reducing total power consumption.
I would like to know how to go about doing this.
Any kind of suggestion would be very beneficial for me.