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There is nothing in the intel spec sheet for this board that says that Hardware Flow Control is or isn't supported. They do give a port diagram with the pin ...
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    There is nothing in the intel spec sheet for this board that says that Hardware Flow Control is or isn't supported. They do give a port diagram with the pin numbers and voltages and the CTS pin is shown. We have two of these boards, and both of them have the same exact behavior, so I don't find it likely that the port is damaged.

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    Quote Originally Posted by JHenson View Post
    There is nothing in the intel spec sheet for this board that says that Hardware Flow Control is or isn't supported. They do give a port diagram with the pin numbers and voltages and the CTS pin is shown. We have two of these boards, and both of them have the same exact behavior, so I don't find it likely that the port is damaged.
    Then I think it has to be an issue of DTE vs DCE. It seems to me that it is configured as a Data Terminal Equipment (DTE) device.
    Sometimes, real fast is almost as good as real time.
    Just remember, Semper Gumbi - always be flexible!

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    Quote Originally Posted by Rubberman View Post
    Then I think it has to be an issue of DTE vs DCE. It seems to me that it is configured as a Data Terminal Equipment (DTE) device.
    Then, what does this mean for me, how do I make it work with the CTS pin?

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    Quote Originally Posted by Rubberman View Post
    Then I think it has to be an issue of DTE vs DCE. It seems to me that it is configured as a Data Terminal Equipment (DTE) device.
    Ok, I think I understand what you are saying now. However, if it is DTE only, how come I can receive the DSR bit? Also, I need to use these bits, because I am using them to detect and respond to switches on a circuit board. I know this isn't the typical usage of a serial port, but it seems odd to me that the only boards this won't work on are these Intel boards.

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    Ok, I found it. The Jetway board com header was laid out as

    6 7 8 9
    x x x x
    x x x x x
    1 2 3 4 5

    while the Intel was laid out as:

    2 4 6 8
    x x x x
    x x x x x
    1 3 5 7 9

    Why there are two variations of com headers makes no sense to me. Anyhow thanks for all the help.

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