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Thread: Makefile

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  1. #1


    I am banging my head trying to get a certain kind of Makefile to work. Here is what I have so far.

    CXX  = g++
    LIBS = -L$(SYSTEMC_HOME)/lib-$(TARGET_ARCH) -lsystemc
    INC  = -I$(SYSTEMC_HOME)/include
    SOURCES = file1.cpp file2.cpp
    	$(CXX) $(INC) -c file1.cpp
    	$(CXX) $(INC) -c file2.cpp
    .PHONY: clean
    	rm -f *.o
    Note I am only building objects at this point. I want to make this work in a general way so I only have to add new source files (i.e. file3.cpp) to the $SOURCES variable instead of adding a new "file3.o:" line. I've tried various things I have googled but it isn't working how I want. I am either seeing strange results (errors) or compiling each file at once which isn't what I want either. Can someone help please?

  2. #2
    Linux User
    Join Date
    Jun 2012
    SF Bay area
    Here's a Makefile I came up with a couple of months ago that seems related to what you're trying to do. I can just add a program name to the list at the time and all the rules to compile and link work for whichever one I "make". You might be able to copy bits and pieces out.

    PROGS = capture-udp-port send-udp-message capture-udpv6-port send-udpv6-message capture-udp-port-hex capture-udpv6-port-hex
    # ---
    CC = gcc
    LD = gcc
    CFLAGS = -g -Wall -pedantic
    LDFLAGS = 
    # ---
    	@echo "You can make any of the following programs: $(PROGS)"
    # ---
    .PHONY: all
    all: $(PROGS)
    # ---
    %.o : %.c Makefile
    	$(CC) -c -o $@ $(CFLAGS) $<
    $(PROGS) : % : %.o
    	$(CC) -o $@ $(@).o $(LDFLAGS)
    # ---
    	rm $(PROGS) *.o

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