Makefiles...

[ejohns85]

Hello,

I am new to the whole concept of makefiles, and I'm trying to compile and build my program using a makefile template I have found. My project consists of three directories: "source", where my .cpp files are (source1.cpp, source2.cpp, source3.cpp), "include", where my .h files are (header1.h, header2.h, header3.h), and "obj", where the object files are to be stored (obj1.o, obj2.o, obj3.o). In the project root directory is my makefile, which is as follows:

(please note that I have replaced the at keyboard symbol with "at", otherwise the post is rejected)

EXEC = myexe
CC = g++
IDIR = include
SDIR = source
ODIR = obj
LDIR= -L
LIBS= -l
CFLAGS = -I$(IDIR1) $(LDIR) $(LIBS)

_DEPS = header1.h header2.h header3.h
DEPS = $(patsubst %,$(IDIR)/%,$(_DEPS))

_OBJ = obj1.h obj2.h obj3.h
OBJ = $(patsubst %,$(ODIR)/%,$(_OBJ))

$(ODIR)/%.o: $(SDIR)/%.cpp $(DEPS)
	$(CC) -c -o $"at" $< $(CFLAGS)

$(EXEC): $(OBJ)
	$(CC) -o $"at" $^ $(CFLAGS) $(LDIR) $(LIBS)

clean:
	rm -f $(ODIR)/*.o *~ core $(INCDIR)/*~

However, when I try to "make" my program, I get the following error:

"make: *** No rule to make target `obj/obj1.o', needed by `myexe'. Stop."

But as far as I can see, this rule is present, in the line

$(ODIR)/%.o: $(SDIR)/%.cpp $(DEPS)
	$(CC) -c -o $"at" $< $(CFLAGS)

Have I made some errors in the makefile, or is it a different problem?

Thanks!

[alf55]

Here is a break down of the makefiile

EXEC = myexe
CC = g++
IDIR = include
SDIR = source
ODIR = obj
LDIR= -L
LIBS= -l
CFLAGS = -I$(IDIR1) $(LDIR) $(LIBS)

The above section is setting variables. In make a variable is de-referenced by the "$(varname)" as used in the CFLAGS and latter on.

_DEPS = header1.h header2.h header3.h
DEPS = $(patsubst %,$(IDIR)/%,$(_DEPS))

Here they are listing all the header files that are created as part of your application. In this skeleton they are:

• header1.h
• header2.h
• header3.h

Then they are used in a "foreach" that changes the list into

• include/header1.h
• include/header2.h
• include/header3.h

So the "DEPS = " line is set to:

DEPS = include/header1.h include/header2.h include/header3.h

_OBJ = obj1.o obj2.o obj3.o
OBJ = $(patsubst %,$(ODIR)/%,$(_OBJ))

Again like the header files, these are for the objects. OBJ would be set to:

• obj/obj1.o
• obj/obj2.o
• obj/obj3.o

$(ODIR)/%.o: $(SDIR)/%.cpp $(DEPS)
	$(CC) -c -o $@ $< $(CFLAGS)

A templated "target rule".
The first line is a "target" and the items after the ":" are its dependencies. This one is written as "template" to handle compiling a "source/filename.cpp" into the file "obj/filename.o" via the command:

   g++  -c -o obj/filename.o source/filename.cpp include/header1.h include/header2.h include/header3.h

This target is used as the "rule" to convert from a ".cpp" (source) file into a ".o" (object) file for any of your *.cpp files.

$(EXEC): $(OBJ)
	$(CC) -o $@ $^ $(CFLAGS) $(LDIR) $(LIBS)

This is the "Target Rule" is created to combine the objects into an executable. In this case it creates the file "myexe" from the objects

• obj/obj1.o
• obj/obj2.o
• obj/obj3.o

Via the command:

    g++ -o myexec obj/obj1.o obj/obj2.o obj/obj3.o

clean:
	rm -f $(ODIR)/*.o *~ core $(INCDIR)/*~

This is a "target rule" that can be used to remove the non-source (except for the executable "myexec").


The problem that you are seeing is that the first target rule defined is the the default target to start the build process. Since this is normally to build an executable, and people like to have standard ways to build. The first target is usually "all: $(EXEC)" and it does not need any commands to build it.

Also important is that the command in a "target rule" must start with a real "tab" character.

This template of a make file assumes that you have the following source tree files:

• include/header1.h
• include/header2.h
• include/header3.h
• source/obj1.cpp
• source/obj2.cpp
• source/obj3.cpp
• obj/
• Makefile

Where the make file is:

EXEC = myexe
CC = g++
IDIR = include
SDIR = source
ODIR = obj
LDIR= -L
LIBS= -l
CFLAGS = -I$(IDIR1) $(LDIR) $(LIBS)

_DEPS = header1.h header2.h header3.h
DEPS = $(patsubst %,$(IDIR)/%,$(_DEPS))

DEPS = include/header1.h include/header2.h include/header3.h

_OBJ = obj1.h obj2.h obj3.h
OBJ = $(patsubst %,$(ODIR)/%,$(_OBJ))

all: $(EXEC)


$(ODIR)/%.o: $(SDIR)/%.cpp $(DEPS)
	$(CC) -c -o $@" $< $(CFLAGS)

$(EXEC): $(OBJ)
	$(CC) -o $@ $^ $(CFLAGS) $(LDIR) $(LIBS)

Now you can simple execute:

make

or

make all

to build the executable. While doing

make clean

would execute the command:

rm -f obj/*.o *~ core include/*~

[user-f11]

IMV you cannot just 'find makefile templates'.

1. See whether you have installed a SDK (software development kit) on your computer, read any details about it, etc.

2. You may also take a look at this:
MakeFile - OpenOffice.org Wiki

3. See on the net whether there isn't already any package developed for your case (your distro, your computer platform, your application purposes) - to avoid eventually polluting Internet with redundant software developments.

4. Good luck.